1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device with a π-shaped semiconductor conductive layer and a method for manufacturing the same.
2. Description of the Related Art
In order to achieve high integration density, high speed, and low cost, conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) have entered the nano-era. However, the conventional MOSFETs may encounter serious short-channel effects (SCEs), such as the so-called threshold voltage roll-off phenomenon and drain-induced barrier lowering (DIBL) effects. In addition, a conventional bulk complementary metal oxide semiconductor (CMOS) also has problems including excessive PN junction parasitic capacitance and serious leakage current.
A silicon-on-insulator (SOI) technique seems to alleviate all the problems of the conventional bulk CMOS. However, the conventional SOI faces the problems of serious floating-body effects (FBEs) and poor heat dissipation. If better element subthreshold characteristics are to be obtained, the thickness of the main body of the conventional SOI must be further reduced, which will result in more serious self-heating effects (SHEs) and greatly lower the heat stability of the element, and the uneven thinness of the silicon film corresponding to the series resistance and the threshold voltage seriously will affect the element performance. In addition, an improved MOSFET manufactured by utilizing a non self-aligned technique defines a silicon main body and a gate by using a plurality of masks, which makes it difficult to keep the compact size or achieve mass production.
Therefore, it is necessary to provide a semiconductor device with a π-shaped semiconductor conductive layer and a method for manufacturing the same, so as to solve the above problems.